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voltage-to-frequency and frequency-to-voltage converter ad650 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features v/f conversion to 1 mhz reliable monolithic construction very low nonlinearity 0.002% typ at 10 khz 0.005% typ at 100 khz 0.07% typ at 1 mhz input offset trimmable to zero cmos- or ttl-compatible unipolar, bipolar, or differential v/f v/f or f/v conversion available in surface mount mil-std-883 compliant versions available functional block diagram 00797-001 op amp comp in freq out out one shot 8 f output 9 comparator input 10 digital gnd 11 analog gnd 12 +v s 13 offset null 7 nc 6 one shot c apacitor 5 ?v s 4 bipolar offset current 3 ?in 2 +in 1 v out 14 offset null input offset trim ?0.6v ad650 ?v s ?v s 1ma s1 nc = no connect figure 1. product description the ad650 v/f/v (voltage-to-frequency or frequency-to-voltage converter) provides a combination of high frequency operation and low nonlinearity previously unavailable in monolithic form. the inherent monotonicity of the v/f transfer function makes the ad650 useful as a high-resolution analog-to-digital converter. a flexible input configuration allows a wide variety of input voltage and current formats to be used, and an open-collector output with separate digital ground allows simple interfacing to either standard logic families or opto-couplers. the linearity error of the ad650 is typically 20 ppm (0.002% of full scale) and 50 ppm (0.005%) maximum at 10 khz full scale. this corresponds to approximately 14-bit linearity in an analog- to-digital converter circuit. higher full-scale frequencies or longer count intervals can be used for higher resolution conversions. the ad650 has a useful dynamic range of six decades allowing extremely high resolution measurements. even at 1 mhz full scale, linearity is guaranteed less than 1000 ppm (0.1%) on the ad650kn, bd, and sd grades. in addition to analog-to-digi tal conversion, the ad650 can be used in isolated analog signal transmission applications, phased-locked loop circuits, and precision stepper motor speed controllers. in the f/v mode, the ad650 can be used in precision tachometer and fm demodulator circuits. the input signal range and full-scale output frequency are user- programmable with two external capacitors and one resistor. input offset voltage can be trimmed to zero with an external potentiometer. the ad650jn and ad650kn are offered in plastic 14-lead dip packages. the ad650jp is available in a 20-lead plastic leaded chip carrier (plcc). both plastic packaged versions of the ad650 are specified for the commercial temperature range (0c to 70c). for industrial temperature range (?25c to +85c) applications, the ad650ad and ad650bd are offered in ceramic packages. the ad650sd is specified for the full ?55c to +125c extended temperature range. product highlights 1. can operate at full-scale output frequencies up to 1 mhz (in addition to having very high linearity). 2. can be configured to accommodate bipolar, unipolar, or differential input voltages, or unipolar input currents. 3. ttl or cmos compatibility is achieved by using an open collector frequency output. the pull-up resistor can be connected to voltages up to 30 v. 4. the same components used for v/f conversion can also be used for f/v conversion by adding a simple logic biasing network and reconfiguring the ad650. 5. separate analog and digital grounds prevent ground loops in real-world applications. 6. available in versions compliant with mil-std-883.
ad650 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 product description......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 circuit operation ............................................................................. 7 unipolar configuration............................................................... 7 component selection................................................................... 8 bipolar v/f .................................................................................. 10 unipolar v/f, negative input voltage ..................................... 10 f/v conversion .......................................................................... 10 high frequency operation ....................................................... 10 decoupling and grounding...................................................... 12 temperature coefficients.......................................................... 12 nonlinearity specification ........................................................ 13 psrr............................................................................................. 14 other circuit considerations ................................................... 14 applications..................................................................................... 16 differential voltage-to-frequency conversion...................... 16 autozero circuit......................................................................... 16 phase-locked loop f/v conversion ...................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 3/06rev. c to rev. d updated format..................................................................universal changes to product highlights....................................................... 1 changes to table 1............................................................................ 3 added pin function descriptions table ...................................... 6 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 19
ad650 rev. d | page 3 of 20 specifications t = 25c, v s = 15 v, unless otherwise noted. table 1. ad650j/ad650a ad650k/ad650b ad650s model min typ max min typ max min typ max units dynamic performance full-scale frequency range 1 1 1 mhz nonlinearity 1 f max = 10 khz 0.002 0.005 0.002 0.005 0.002 0.005 % f max = 100 khz 0.005 0.02 0.005 0.02 0.005 0.02 % f max = 500 khz 0.02 0.05 0.02 0.05 0.02 0.05 % f max = 1 mhz 0.1 0.05 0.1 0.05 0.1 % full-scale calibration error 2 100 khz 5 5 5 % 1 mhz 10 10 10 % vs. supply 3 ?0.015 +0.015 ?0.015 +0.015 ?0.015 +0.015 % of fsr/v vs. temperature a, b, and s grades at 10 khz 75 75 75 ppm/c at 100 khz 150 150 200 ppm/c j and k grades at 10 khz 75 75 ppm/c at 100 khz 150 150 ppm/c bipolar offset current activated by 1.24 k between pin 4 and pin 5 0.45 0.5 0.55 0.45 0.5 0.55 0.45 0.5 0.55 ma dynamic response maximum settling time for full-scale step input 1 pulse of new frequency plus 1 s 1 pulse of new frequency plus 1 s 1 pulse of new frequency plus 1 s overload recovery time step input 1 pulse of new frequency plus 1 s 1 pulse of new frequency plus 1 s 1 pulse of new frequency plus 1 s analog input amplifier (v/f conversion) current input range ( figure 4 ) 0 +0.6 0 +0.6 0 +0.6 ma voltage input range ( figure 12 ) ?10 0 ?10 0 ?10 0 v differential impedance 2 m||10 pf 2 m||10 pf 2 m||10 pf common-mode impedance 1000 m||10 pf 1000 m||10 pf 1000 m||10 pf input bias current noninverting input 40 100 40 100 40 100 na inverting input 8 20 8 20 8 20 na input offset voltage (trimmable to zero) 4 4 4 mv vs. temperature (t min to t max ) 30 30 30 v/c safe input voltage v s v s v s v comparator (f/v conversion) logic 0 level ?v s ?1 ?v s ?1 ?v s ?1 v logic 1 level 0 +v s 0 +v s 0 +v s v pulse width range 4 0.1 (0.3 t os ) 0.1 (0.3 t os ) 0.1 (0.3 t os ) s input impedance 250 250 250 k open collector output (v/f conversion) output voltage in logic 0 i sink 8 ma, t min to t max 0.4 0.4 0.4 v output leakage current in logic 1 100 100 100 na voltage range 5 0 36 0 36 0 36 v
ad650 rev. d | page 4 of 20 ad650j/ad650a ad650k/ad650b ad650s model min typ max min typ max min typ max units amplifier output (f/v conversion) voltage range (1500 min load resistance) 0 10 0 10 0 10 v source current (750 max load resistance) 10 10 10 ma capacitive load (without oscillation) 100 100 100 pf power supply voltage, rated performance 9 18 9 18 9 18 v quiescent current 8 8 8 ma temperature range rated performance n package 0 +70 0 +70 c d package ?25 +85 ?25 +85 ?55 +125 c 1 nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale. 2 full-scale calibration error adjustable to zero. 3 measured at full-scale ou tput frequency of 100 khz. 4 refer to f/v conversion section of the text. 5 referred to digital ground. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality l evels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ad650 rev. d | page 5 of 20 absolute maximum ratings parameter rating total supply voltage 36 v storage temperature range ?55c to +150c differential input voltage 10 v maximum input voltage v s open collector output voltage above digital gnd 36 v current 50 ma amplifier short circuit to ground indefinite comparator input voltage v s stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad650 rev. d | page 6 of 20 pin configurations and function descriptions v out 1 +in 2 ?in 3 bibolar offset current 4 offset null 14 offset null 13 +v s 12 analog gnd 11 ?v s 5 digital gnd 10 one shot capacitor 6 comparator input 9 nc 7 f output 8 nc = no connect ad650 top view (not to scale) 00797-010 figure 2. d-14, n-14 pin configurations 12019 23 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 nc = no connect ?in nc bipolar offset current nc ?v s +v s nc analog gnd nc digital gnd +in v out nc offset null offset null one shot capacitor nc nc f output comparator input pin 1 indentfier ad650 top view (not to scale) 00797-011 figure 3. p-20a pin configuration table 2. pin function descriptions pin no. d-14, n-14 p-20a mnemonic description 1 2 v out output of operational amplifier. the operational amplifier, along with c int , is used in the integrate stage of the v to f conversion. 2 3 +in positive analog input. 3 4 Cin negative analog input. 4 6 bipolar offset current on-chip current source. this can be us ed in conjunction with an external resistor to remove the operational amplifiers offset. 5 8 Cv s negative power supply input. 6 9 one-shot capacitor the capacitor, c os , is connected to this pin. c os determines the time period for the one shot. 7 1, 5, 7, 10, 11, 15, 17 nc no connect. 8 12 f output frequency output from ad650. 9 13 comparator input input to comparator. when the input voltage reaches ?0.6 v, the one shot is triggered. 10 14 digital gnd digital ground. 11 16 analog gnd analog ground. 12 18 +v s positive power supply input. 13, 14 19, 20 offset null offset null pins. using an external potentiometer, the offset of the operational amplifier can be removed.
ad650 rev. d | page 7 of 20 circuit operation unipolar configuration the ad650 is a charge balance voltage-to-frequency converter. in the connection diagram shown in figure 4 , or the block diagram of figure 5 , the input signal is converted into an equivalent current by the input resistance r in . this current is exactly balanced by an internal feedback current delivered in short, timed bursts from the switched 1 ma internal current source. these bursts of current can be thought of as precisely defined packets of charge. the required number of charge packets, each producing one pulse of the output transistor, depends upon the amplitude of the input signal. because the number of charge packets delivered per unit time is dependent on the input signal amplitude, a linear voltage-to-frequency transformation is accomplished. the frequency output is furnished via an open collector transistor. a more rigorous analysis demonstrates how the charge balance voltage-to-frequency conversion takes place. a block diagram of the device arranged as a v-to-f converter is shown in figure 5 . the unit is comprised of an input integrator, a current source and steering switch, a comparator, and a one shot. when the output of the one shot is low, the current steering switch s 1 diverts all the current to the output of the op amp; this is called the integration period. when the one shot has been triggered and its output is high, the switch s 1 diverts all the current to the summing junction of the op amp; this is called the reset period. the two different states are shown in figure 6 and figure 7 along with the various branch currents. it should be noted that the output current from the op amp is the same for either state, thus minimizing transients. 0 0797-003 op amp comp in freq out out one shot 8 9 10 11 12 13 7 ?15v 0.1f c os 6 4 2 1 14 input offset trim ?0.6v ad650 ?v s ?v s 1ma s1 5 f out v logic +15v v in r3 r1 r in 3 digital ground analog ground 1f 250k ? 20k ? r2 0.1f c int figure 4. connection diagram for v/f conversion, positive input voltage 00797-004 v in ?v s s1 1ma 20% ad650 + ? r in i in c int integrator ?0.6v comparator frequency output one shot c os t t os figure 5. block diagram 00797-005 v in ?v s s1 1ma + ? r in i in c int 1ma ? i in 1ma figure 6. reset mode 00797-006 v in ?v s s1 1ma + ? r in i in c int 1ma ? i in i in 1ma figure 7. integrate mode 0 0797-007 reset integrate ? 0.6 v volts t os t 1 t figure 8. voltage across c int
ad650 rev. d | page 8 of 20 the positive input voltage develops a current (i in = v in /r in ) that charges the integrator capacitor c int . as charge builds up on c int , the output voltage of the integrator ramps downward towards ground. when the integrator output voltage (pin 1) crosses the comparator threshold (C0.6 v) the comparator triggers the one shot, whose time period, t os is determined by the one-shot capacitor c os . specifically, the one-shot time period is sec100.3f/sec108.6 7 3 ? + = os os ct (1) the reset period is initiated as soon as the integrator output voltage crosses the comparator threshold, and the integrator ramps upward by an amount ( in int os os i c ) t dt dv tv ? == ma1 (2) after the reset period has ended, the device starts another integration period, as shown in figure 8 , and starts ramping downward again. the amount of time required to reach the comparator threshold is given as () ? ? ? ? ? ? ? ? ? = ? = = 1 ma1 ma1 1 in os int n in int os i t c i i c t dt dv v t (3) the output frequency is now given as f c rv a f t i tt f os inin os in os out 11 1 104.4 / hz 15.0 ma1 1 ? + = = + = (4) note that c int , the integration capacitor, has no effect on the transfer relation, but merely determines the amplitude of the sawtooth signal out of the integrator. one-shot timing a key part of the preceding analysis is the one-shot time period given in equation 1. this time period can be broken down into approximately 300 ns of propagation delay and a second time segment dependent linearly on timing capacitor c os . when the one shot is triggered, a voltage switch that holds pin 6 at analog ground is opened, allowing that voltage to change. an internal 0.5 ma current source connected to pin 6 then draws its current out of c os , causing the voltage at pin 6 to decrease linearly. at approximately C3.4 v, the one shot resets itself, thereby ending the timed period and starting the v/f conversion cycle over again. the total one-shot time period can be written mathematically as delay gate discharge os os t i cv t + = (5) substituting actual values quoted in equation 5, sec10300 a105.0 v4.3 9 3 ? ? + ? ? = os os c t (6) this simplifies into the timed period equation (see equation 1). component selection only four component values must be selected by the user. these are input resistance r in , timing capacitor c os , logic resistor r2, and integration capacitor c int . the first two determine the input voltage and full-scale frequency, while the last two are determined by other circuit considerations. of the four components to be selected, r2 is the easiest to define. as a pull-up resistor, it should be chosen to limit the current through the output transistor to 8 ma if a ttl maximum v ol of 0.4 v is desired. for example, if a 5 v logic supply is used, r2 should be no smaller than 5 v/8 ma or 625 . a larger value can be used if desired. r in and c os are the only two parameters available to set the full- scale frequency to accommodate the given signal range. the swing variable that is affected by the choice of r in and c os is nonlinearity. the selection guides of figure 9 and figure 10 show this quite graphically. in general, larger values of c os and lower full-scale input currents (higher values of r in ) provide better linearity. in figure 10 , the implications of four different choices of r in are shown. although the selection guide is set up for a unipolar configuration with a 0 v to 10 v input signal range, the results can be extended to other configurations and input signal ranges. for a full-scale frequency of 100 khz (corresponding to 10 v input), among the available choices r in = 20 k and c os = 620 pf gives the lowest nonlinearity, 0.0038%. in addition, the highest frequency that gives the 20 ppm minimum nonlinearity is approximately 33 khz (40.2 k and 1000 pf). for input signal spans other than 10 v, the input resistance must be scaled proportionately. for example, if 100 k is called out for a 0 v to 10 v span, 10 k would be used with a 0 v to 1 v span, or 200 k with a 10 v bipolar connection. the last component to be selected is the integration capacitor c int . in almost all cases, the best value for c int can be calculated using the equation ( minimum pf1000 sec/10 4 ) m a x int f f c ? = (7) when the proper value for c int is used, the charge balance architecture of the ad650 provides continuous integration of the input signal, therefore, large amounts of noise and interference can be rejected. if the output frequency is measured by counting pulses during a constant gate period, the integration provides infinite normal-mode rejection for frequencies corresponding to the gate period and its harmonics. however, if the integrator stage becomes saturated by an excessively large noise pulse, then the continuous integration of the signal is interrupted, allowing the noise to appear at the output.
ad650 rev. d | page 9 of 20 if the approximate amount of noise that appears on c int is known (v noise ), then the value of c int can be checked using the following inequality: noise s os int vv a t c ??+ > ? v3 101 3 (8) for example, consider an application calling for a maximum frequency of 75 khz, a 0 v to 1 v signal range, and supply voltages of only 9 v. the component selection guide of figure 9 is used to select 2.0 k for r in and 1000 pf for c os . this results in a one-shot time period of approximately 7 s. substituting 75 khz into equation 7 yields a value of 1300 pf for c int . when the input signal is near zero, 1 ma flows through the integration capacitor to the switched current sink during the reset phase, causing the voltage across c int to increase by approximately 5.5 v. because the integrator output stage requires approximately 3 v headroom for proper operation, only 0.5 v margin remains for integrating extraneous noise on the signal line. a negative noise pulse at this time could saturate the integrator, causing an error in signal integration. increasing c int to 1500 pf or 2000 pf provides much more noise margin, thereby eliminating this potential trouble spot. 1mhz 100khz 10khz 50 100 1000 frequency full-scale c os (pf) 00797-008 input resistor 16.9k 20k 40.2k 100k figure 9. full-sca le frequency vs. c os 100 20 50 100 1000 typical nonlinearity (ppm) one shot capacitor c os (pf) 1000 input resistor 16.9k 40.2k 100k 20k 00797-009 figure 10. typical nonlinearity vs. c os
ad650 rev. d | page 10 of 20 bipolar v/f figure 11 shows how the internal bipolar current sink is used to p rovide a half-scale offset for a 5 v signal range, while providing a 100 khz maximum output frequency. the nominally 0.5 ma (10%) offset current sink is enabled when a 1.24 k resistor is connected between pin 4 and pin 5. thus, with the grounded 10 k nominal resistance shown, a ?5 v offset is developed at pin 2. because pin 3 must also be at ?5 v, the current through r in is 10 v/40 k = +0.25 ma at v in = +5 v, and 0 ma at v in = C5 v. components are selected using the same guidelines outlined for t he unipolar configuration with one alteration. the voltage across the total signal range must be equated to the maximum input voltage in the unipolar configuration. in other words, the value of the input resistor r in is determined by the input voltage span, not the maximum input voltage. a diode from pin 1 to ground is also recommended. this is further discussed in the other circuit considerations section. as in the unipolar circuit, r in and c os must have low temperature coefficients to minimize the overall gain drift. the 1.24 k resistor used to activate the 0.5 ma offset current should also have a low temperature coefficient. the bipolar offset current has a temperature coefficient of approximately ?200 ppm/c. unipolar v/f, negative input voltage figure 12 shows the connection diagram for v/f conversion of n egative input voltages. in this configuration, full-scale output frequency occurs at negative full-scale input, and zero output frequency corresponds with zero input voltage. a very high impedance signal source can be used because it only d rives the noninverting integrator input. typical input impedance at this terminal is 1 g or higher. for v/f conversion of positive input signals using the connection diagram of figure 4 , the signal g enerator must be able to source the integration current to drive the ad650. for the negative v/f conversion circuit of figure 12 , the integration current is drawn from ground t hrough r1 and r3, and the active input is high impedance. circuit operation for negative input voltages is very similar to p ositive input unipolar conversion described in the unipolar c onfiguration section. for best operating results use equation 7 an d equation 8 in the component selection section. f/v conversion the ad650 also makes a very linear frequency-to-voltage converter. figure 13 shows the connection diagram for f/v co nversion with ttl input logic levels. each time the input signal crosses the comparator threshold going negative, the one shot is activated and switches 1 ma into the integrator input for a measured time period (determined by c os ). as the frequency increases, the amount of charge injected into the integration capacitor increases proportionately. the voltage across the integration capacitor is stabilized when the leakage current through r1 and r3 equals the average current being switched into the integrator. the net result of these two effects is an average output voltage that is proportional to the input frequency. optimum performance can be obtained by selecting components using the same guidelines and equations listed in the bipolar v/f section. for a more complete description of this application, refer to ana log devices application note an-279. high frequency operation proper rf techniques must be observed when operating the ad650 at or near its maximum frequency of 1 mhz. lead lengths must be kept as short as possible, especially on the one shot and integration capacitors, and at the integrator summing junction. in addition, at maximum output frequencies above 500 khz, a 3.6 k pull-down resistor from pin 1 to ?v s is required (see figure 14 ). the additional current drawn through t he pulldown resistor reduces the op amps output impedance and improves its transient response. 00797-012 op amp comp in freq out out one shot 8 9 10 11 13 12 7 6 5 4 3 2 1 14 input offset trim ?0.6v ad650 ?v s ?v s 1ma s1 c os 330pf ?15v 0.1f v in 5 v 1.24k ? r3 37.4k ? 10k ? r1 5k ? c int 1000pf 20k ? 250k ? 0.1f 1f 1k ? +15v +5v digital gnd analog gnd f out figure 11. connections for 5 v bipolar v/f with 0 khz to 100 khz ttl output
ad650 rev. d | page 11 of 20 00797-013 op amp comp in freq out out one shot 8 9 10 11 13 12 7 6 5 4 3 2 1 14 input offset trim ?0.6v ad650 ?v s ?v s 1ma s1 c os ?15v 0.1f ?v in r1 r3 c int 20k ? 250k ? 0.1f 1f r2 +15v +v logic digital gnd analog gnd f out figure 12. connection diagram for v/f conversion, negative input voltage 00797-014 op amp comp in freq out out one shot 8 9 10 11 13 12 7 6 5 4 3 2 1 14 input offset trim ?0.6v ad650 ?v s ?v s 1ma s1 c os ?15v 0.1f 20k ? 250k ? 0.1f +15v v out +5v analog gnd f in 2k ? 500 ? 500 ? 560pf r1 r3 c int 1n914 figure 13. connection diagram for f/v conversion 00797-015 op amp comp in freq out out one shot 8 9 10 11 13 12 7 6 5 4 3 2 1 14 input offset trim ?0.6v ad650 ?v s ?v s 1ma s1 51pf ?15v 0.1f 1000pf 20k ? 250k ? 510 ? 0.1f +15v offset adjust analog gnd plane digital gnd f out 0mhz to 1mhz +5v 1f 3.6k ? 14.3k ? v in 0v to 10v gain adjust 5k ? figure 14. 1 mhz v/f connection diagram
ad650 rev. d | page 12 of 20 decoupling and grounding it is effective engineering practice to use bypass capacitors on the supply-voltage pins and to insert small-valued resistors (10 to 100 ) in the supply lines to provide a measure of decoupling between the various circuits in a system. ceramic capacitors of 0.1 f to 1.0 f should be applied between the supply-voltage pins and analog signal ground for proper bypassing on the ad650. in addition, a larger board level decoupling capacitor of 1 f to 10 f should be located relatively close to the ad650 on each power supply line. such precautions are imperative in high resolution, data acquisition applications where users expect to exploit the full linearity and dynamic range of the ad650. although some types of circuits can operate satisfactorily with power supply decoupling at only one location on each circuit board, such practice is strongly discouraged in high accuracy analog design. separate digital and analog grounds are provided on the ad650. the emitter of the open collector frequency output transistor is the only node returned to the digital ground. all other signals are referred to analog ground. the purpose of the two separate grounds is to allow isolation between the high precision analog signals and the digital section of the circuitry. as much as several hundred millivolts of noise can be tolerated on the digital ground without affecting the accuracy of the vfc. such ground noise is inevitable when switching the large currents associated with the frequency output signal. at 1 mhz full scale, it is necessary to use a pull-up resistor of about 500 in order to get the rise time fast enough to provide well defined output pulses. this means that from a 5 v logic supply, for example, the open collector output draws 10 ma. this much current being switched causes ringing on long ground runs due to the self-inductance of the wires. for instance, 20 gauge wire has an inductance of about 20 nh per inch; a current of 10 ma being switched in 50 ns at the end of 12 inches of 20 gauge wire produces a voltage spike of 50 mv. the separate digital ground of the ad650 easily handles these types of switching transients. a problem remains from interference caused by radiation of electromagnetic energy from these fast transients. typically, a voltage spike is produced by inductive switching transients; these spikes can capacitively couple into other sections of the circuit. another problem is ringing of ground lines and power supply lines due to the distributed capacitance and inductance of the wires. such ringing can also couple interference into sensitive analog circuits. the best solution to these problems is proper bypassing of the logic supply at the ad650 package. a 1 f to 10 f tantalum capacitor should be connected directly to the supply side of the pull-up resistor and to the digital ground (pin 10). the pull-up resistor should be connected directly to the frequency output (pin 8). the lead lengths on the bypass capacitor and the pull-up resistor should be as short as possible. the capacitor supplies (or absorbs) the current transients, and large ac signals flows in a physically small loop through the capacitor, pull-up resistor, and frequency output transistor. it is important that the loop be physically small for two reasons: first, there is less self-inductance if the wires are short, and second, the loop does not radiate rfi efficiently. the digital ground (pin 10) should be separately connected to the power supply ground. note that the leads to the digital power supply are only carrying dc current and cannot radiate rfi. there can also be a dc ground drop due to the difference in currents returned on the analog and digital grounds. this does not cause any problem. in fact, the ad650 tolerates as much as 0.25 v dc potential difference between the analog and digital grounds. these features greatly ease power distribution and ground management in large systems. proper technique for grounding requires separate digital and analog ground returns to the power supply. also, the signal ground must be referred directly to analog ground (pin 11) at the package. all of the signal grounds should be tied directly to pin 11, especially the one-shot capacitor. more information on proper grounding and reduction of interference can be found in noise reduction techniques in electronic systems, 2 nd edition by henry w. ott, (john wiley & sons, inc., 1988). temperature coefficients the drift specifications of the ad650 do not include temperature effects of any of the supporting resistors or capacitors. the drift of the input resistors r1 and r3 and the timing capacitor c os directly affect the overall temperature stability. in the application of figure 5 , a 10 ppm/c input resistor used with a 100 ppm/c capacitor can result in a maximum overall circuit gain drift of: 150 ppm/c (ad650a) + 100 ppm/c (c os ) + 10 ppm/c (r in ) = 260 ppm/c in bipolar configuration, the drift of the 1.24 k resistor used to activate the internal bipolar offset current source directly affects the value of this current. this resistor should be matched to the resistor connected to the op amp noninverting input, pin 2 (see figure 11 ). that is, the temperature coefficients of these two resistors should be equal. if this is the case, then the effects of the temperature coefficients of the resistors cancel each other, and the drift of the offset voltage developed at the op amp noninverting input is solely determined by the ad650. under these conditions, the tc of the bipolar offset voltage is typically ?200 ppm/c and is a maximum of ?300 ppm/c. the offset voltage always decreases in magnitude as temperature is increased.
ad650 rev. d | page 13 of 20 other circuit components do not directly influence the accuracy of the vfc over temperature changes as long as their actual values are not as different from the nominal value as to preclude operation. this includes the integration capacitor c int . a change in the capacitance value of c int simply results in a different rate of voltage change across the capacitor. during the integration phase (see figure 8 ), the rate of voltage change across c int has the opposite effect that it does during the reset phase. the result is that the conversion accuracy is unchanged by either drift or tolerance of c int . the net effect of a change in the integrator capacitor is simply to change the peak-to-peak amplitude of the sawtooth waveform at the output of the integrator. the gain temperature coefficient of the ad650 is not a constant value. rather, the gain tc is a function of both the full-scale frequency and the ambient temperature. at a low full-scale frequency, the gain tc is determined primarily by the stability of the internal reference (a buried zener reference). this low speed gain tc can be quite effective; at 10 khz full scale, the gain tc near 25c is typically 0 50 ppm/c. although the gain tc changes with ambient temperature (tending to be more positive at higher temperatures), the drift remains within a 75 ppm/c window over the entire military temperature range. at full-scale frequencies higher than 10 khz, dynamic errors become much more important than the static drift of the dc reference. at a full-scale frequency of 100 khz and above, these timing errors dominate the gain tc. for example, at 100 khz full-scale frequency (r in = 40 k and c os = 330 pf) the gain tc near room temperature is typically ?80 50 ppm/c, but at an ambient temperature near 125c, the gain tc tends to be more positive and is typically 15 50 ppm/c. this information is presented in a graphical form in figure 15 . the gain tc always tends to become more positive at higher temperatures. therefore, it is possible to adjust the gain tc of the ad650 by using a one-shot capacitor with an appropriate tc to cancel the drift of the circuit. for example, consider the 100 khz full-scale frequency. an average drift of ? 100 ppm/c means that as temperature is increased, the circuit produces a lower frequency in response to a given input voltage. this means that the one-shot capacitor must decrease in value as temperature increases in order to compensate the gain tc of the ad650; that is, the capacitor must have a tc of ?100 ppm/c. now consider the 1 mhz full-scale frequency. 100 ?50 10khz 100khz 1mhz ?250 255075 100 125 0 ?100 ?200 ?300 ?400 temperature (c) gain tc (ppm/c) 00797-016 figure 15. gain tc vs. temperature it is not possible to achieve much improvement in performance unless the expected ambient temperature range is known. for example, in a constant low temperature application such as gathering data in an arctic climate (approximately ?20c), a c os with a drift of ?310 ppm/c is called for in order to compensate the gain drift of the ad650. however, if that circuit should see an ambient temperature of 75c, then the c os capacitor would change the gain tc from approximately 0 ppm to 310 ppm/c. the temperature effects of these components are the same when the ad650 is configured for negative or bipolar input voltages, and for f/v conversion as well. nonlinearity specification the linearity error of the ad650 is specified by the endpoint method. that is, the error is expressed in terms of the deviation from the ideal voltage to frequency transfer relation after calibrating the converter at full scale and zero. the nonlinearity varies with the choice of one-shot capacitor and input resistor (see figure 10 ). verification of the linearity specification requires the availability of a switchable voltage source (or a dac) having a linearity error below 20 ppm, and the use of very long measurement intervals to minimize count uncertainties. every ad650 is automatically tested for linearity, and it is not usually necessary to perform this verification, which is both tedious and time consuming. if it is required to perform a nonlinearity test either as part of an incoming quality screening or as a final product evaluation, an automated bench- top tester proves useful. such a system based on analog devices lts-2010 is described in v-f converters demand accurate linearity testing, by l. devito, (electronic design, march 4, 1982). the voltage-to-frequency transfer relation is shown in figure 16 and figure 17 with the nonlinearity exaggerated for clarity. the first step in determining nonlinearity is to connect the endpoints of the operating range (typically at 10 mv and 10 v) with a straight line. this straight line is then the ideal relationship that is desired from the circuit. the second step is to find the difference between this line and the actual response of the circuit at a few points between the endpointstypically ten intermediate points suffices. the difference between the actual and the ideal response is a frequency error measured in hertz. finally, these frequency errors are normalized to the full-scale frequency and expressed either as parts per million of full scale (ppm) or parts per hundred of full scale (%). for example, on a 100 khz full scale, if the maximum frequency error is 5 hz, the nonlinearity is specified as 50 ppm or 0.005%. typically on the 100 khz scale, the nonlinearity is positive and the maximum value occurs at about midscale ( figure 16 ). at higher full-scale frequencies, (500 khz to 1 mhz), the nonlinearity becomes s shaped and the maximum value can be either positive or negative. typically, on the 1 mhz scale (r in = 16.9 k, c os = 51 pf) the nonlinearity is positive below about 2/3 scale and is negative above this point. this is shown graphically in figure 17 .
ad650 rev. d | page 14 of 20 100k 100 10mv actual ideal 50ppm 10v input voltage output frequency (hz) 00797-017 figure 16. exaggerated nonlinearity at 100 khz full scale 1m 1k 10mv actual voltage to frequency transfer relation ideal relation 600ppm 10v input voltage output frequency (hz) 600ppm 00797-018 figure 17. exaggerated nonlinearity at 1 mhz full scale 1k 10 full scale frequency (hz) psrr (ppm/%) 100 10k 100k 1m 00797-019 figure 18. psrr vs. full-scale frequency psrr the power supply rejection ratio is a specification of the change in gain of the ad650 as the power supply voltage is changed. the psrr is expressed in units of parts-per-million change of the gain per percent change of the power supply (ppm/%). for example, consider a vfc with a 10 v input applied and an output frequency of exactly 100 khz when the power supply potential is 15 v. changing the power supply to 12.5 v is a 5 v change out of 30 v, or 16.7%. if the output frequency changes to 99.9 khz, then the gain has changed 0.1% or 1000 ppm. the psrr is 1000 ppm divided by 16.7%, which equals 60 ppm/%. the psrr of the ad650 is a function of the full-scale operating frequency. at low full-scale frequencies the psrr is determined by the stability of the reference circuits in the device and can be very effective. at higher frequencies, there are dynamic errors that become more important than the static reference signals, and consequently the psrr is not quite as effective. the values of psrr are typically 0 20 ppm/% at 10 khz full-scale frequency (r in = 40 k, c os = 3300 pf). at 100 khz (r in = 40 k, c os = 330 pf) the psrr is typically +80 40 ppm/%, and at 1 mhz (r in = 16.9 k, c os = 51 pf) the psrr is +350 50 ppm/%. this information is summarized graphically in figure 18 . other circuit considerations the input amplifier connected to pin 1, pin 2, and pin 3 is not a standard operational amplifier. rather, the design has been optimized for simplicity and high speed. the single largest difference between this amplifier and a normal op amp is the lack of an integrator (or level shift) stage. consequently, the voltage on the output (pin 1) must always be more positive than 2 v below the inputs (pin 2 and pin 3). for example, in the f-to-v conversion mode ( figure 13 ) the noninverting input of the op amp (pin 2) is grounded, which means that the output (pin 1) is not able to go below C2 v. normal operation of the circuit shown in figure 13 never calls for a negative voltage at the output, but users can imagine an arrangement calling for a bipolar output voltage (for example, 10 v) by connecting an extra resistor from pin 3 to a positive voltage. however, this does not work. care should be taken under conditions where a high positive input voltage exists at or before power up. these situations can cause a latch up at the integrator output (pin 1). this is a nondestructive latch and, as such, normal operation can be restored by cycling the power supply. latch up can be prevented by connecting two diodes (for example, 1n914 or 1n4148) as shown in figure 11 , thereby preventing pin 1 from swinging below pin 2.
ad650 rev. d | page 15 of 20 a second major difference is that the output only sinks 1 ma to the negative supply. there is no pulldown stage at the output other than the 1 ma current source used for the v-to-f conversion. the op amp sources a great deal of current from the positive supply, and it is internally protected by current limiting. the output of the op amp can be driven to within 3 v of the positive supply when it is not sourcing external current. when sourcing 10 ma the output voltage can be driven to within 6 v of the positive supply. a third difference between this op amp and a normal device is that the inverting input, pin 3, is bias current compensated and the noninverting input is not bias-current compensated. the bias current at the inverting input is nominally zero, but can be as much as 20 na in either direction. the noninverting input typically has a bias current of 40 na that always flows into the node (an npn input transistor). therefore, it is not possible to match input voltage drops due to bias currents by matching input resistors. the op amp has provisions for trimming the input offset voltage. a potentiometer of 20 k is connected from pin 13 to pin 14 and the wiper is connected to the positive supply through a 250 k resistor. a potential of about 0.6 v is established across the 250 k resistor, and the 3 a current is injected into the null pins. it is also possible to null the op amp offset voltage by using only one of the null pins and by using a bipolar current either into or out of the null pin. the amount of current required is very smalltypically less than 3 a. this technique is shown in the applications section of this data sheet; the autozero circuit uses this technique. the bipolar offset current is activated by connecting a 1.24 k resistor between pin 4 and the negative supply. the resulting current delivered to the op amp noninverting input is nominally 0.5 ma and has a tolerance of 10%. this current is then used to provide an offset voltage when pin 2 is tied to ground through a resistor. the 0.5 ma that appears at pin 2 is also flowing through the 1.24 k resistor. an external resistor is used to activate the bipolar offset current source to provide the lowest tolerance and temperature drift of the resulting offset voltage. it is possible to use other values of resistance between pin 4 and ?v s to obtain a bipolar offset current different from 0.5 ma. figure 19 shows the relationship between the bipolar offset current and the value of the resistor used to activate the source. a ? 200 500 4000 external resistor bipolar offset current 400 600 800 1000 1000 1500 2000 2500 3000 3500 00797-020 figure 19. bipolar offset current vs. external resistor
ad650 rev. d | page 16 of 20 applications differential volt age-to-frequency conversion the circuit in figure 20 accepts a true floating differential input signal. the common-mode input, v cm , can be in the range +15 v to ?5 v with respect to analog ground. the signal input, v in , can be 5 v with respect to the common-mode input. both inputs are low impedance; the source that drives the common- mode input must supply the 0.5 ma drawn by the bipolar offset current source, and the source that drives the signal input must supply the integration current. if less common-mode voltage range is required, then a lower voltage zener can be used. for example, if a 5 v zener is used, the v cm input can be in the range +10 v to ?5 v. if the zener is not used at all, the common-mode range is 5 v with respect to analog ground. if no zener is used, the 10 k pulldown resistor is not needed and the integrator output (pin 1) is connected directly to the comparator input (pin 9). autozero circuit in order to exploit the full dynamic range of the ad650 vfc, very small input voltages need to be converted. for example, a six decade dynamic range based on a full scale of 10 v requires accurate measurement of signals down to 10 v. in these situations, a well-controlled input offset voltage is imperative. a constant offset voltage does not affect dynamic range but simply shifts all of the frequency readings by a few hertz. however, if the offset should change, it is not possible to distinguish between a small change in a small input voltage and a drift of the offset voltage. therefore, the usable dynamic range is less. the circuit shown in figure 21 provides automatic adjustment of the op amp offset voltage. the circuit uses an ad582 sample- and-hold amplifier to control the offset, and the input voltage to the vfc is switched between ground and the signal to be measured via an ad7512 di analog switch. the offset of the ad650 is adjusted by injecting a current intoor drawing a current out ofpin 13. note that only one of the offset null pins is used. during the vfc norm mode, the sha is in the hold mode and the hold capacitor is very large, 0.1 f, which holds the ad650 offset constant for a long period of time. when the circuit is in the autozero mode, the sha is in sample mode and behaves like an op amp. the circuit is a variation of the classical two amplifier servo loop, where the output of the device under test (dut)here the dut is the ad650 op ampis forced to ground by the feedback action of the control amplifierthe sha. because the input of the vfc circuit is connected to ground during the autozero mode, the input current that can flow is determined by the offset voltage of the ad650 op amp. because the output of the integrator stage is forced to ground, it is known that the voltage is not changing (it is equal to ground potential). therefore, if the output of the integrator is constant, its input current must be zero, so the offset voltage has been forced to be zero. note that the output of the dut could have been forced to any convenient voltage other than ground. all that is required is that the output voltage be known to be constant. note also that the effect of the bias current at the inverting input of the ad650 op amp is also mulled in this circuit. the 1000 pf capacitor shunting the 200 k resistor is compensation for the two amplifier servo loop. two integrators in a loop require a single zero for compensation. the 3.6 k resistor from pin 1 of the ad650 to the negative supply is not part of the autozero circuit, but rather, it is required for vfc operation at 1 mhz. 00797-021 op amp comp in freq out out one shot 8 9 10 11 13 12 7 6 5 4 3 2 1 14 input offset trim 10v zener 1n5240 notes 1. v cm is the common mode input +15v to ?5v with respect to analog ground. 2. v in is the signal input 5v with respect to v cm . ?0.6v ad650 ?v s v in v cm inpu t ?v s 1ma s1 20k ? 250k ? 0.1f 1f +15v gnd gnd frequency output 0khz to 100khz ?15v +5v ? + ? + 0.1f ? + 1k ? 10k ? c os 330pf c i 1000pf 1.24k ? 40k ? 10k ? figure 20. differential input
ad650 rev. d | page 17 of 20 phase-locked loop f/v conversion although the f/v conversion technique shown in figure 13 is quite accurate and uses only a few extra components, it is very limited in terms of signal frequency response and carrier feed- through. if the carrier (or input) frequency changes instantaneously, then the output cannot change very rapidly due to the integrator time constant formed by c int and r in . while it is possible to decrease the integrator time constant to provide faster settling of the f-to-v output voltage, the carrier feedthrough then becomes larger. for signal frequency response in excess of 2 khz, a phase-lo cked f/v conversion technique such as the one shown in figure 22 is recommended. in a phase-locked loop circuit, the oscillator is driven to a frequency and phase equal to an input reference signal. in applications such as a synthesizer, the oscillator output frequency is first processed through a programmable divide by n before being applied to the phase detector as feedback. here the oscillator frequency is forced to be equal to n times the reference frequency. it is this frequency output that is the desired output signal and not a voltage. in this case, the ad650 offers compact size and wide dynamic range. 14 13 1 8 6 5 4 2 3 7 9 10 1 2 5 4 3 6 +v s ?v s +v s ad582 ?v s 1000pf cap 0.1f 200k ? 10k ? output 1k ? 1 2 3 4 14 13 12 11 5 10 6 9 7 8 ad7512 ?v s +v s control input +5v input voltage 16.9k ? 0.5ma bipolar offset 1ma ?v s +in ?in +v s c os null ad650 null comparator input comparator frequency output digital gnd analog gnd frequency output one shot op amp ?0.6 volt 500 ? 10f 0.1f 51pf 0.1f + 10 ?15v +15v gnd 1000pf 9 00797-022 3.6k ? ?5 volts vfc normal gnd auto zero 11 12 8 figure 21. autozero circuit c 51pf 15pf r 140k ? 71.5k ? 590k ? ?15v 10 12 4 1 2 11 3 13 9 5 ad650 1mhz full-scale r in = 16.9k c os = 51pf c int = 1000pf (unipolar input) freq out input carrier volts input to ad650 nand xor 1 2 5 4 36 g d b s 1/2 7474 1/2 7474 d 1 pr 1 d 2 pr 2 q 1 q 2 clear 1 sd211 dmosfet d type flip flop 1 1 f/v voltage output input carrier clock 1 clock 2 clear 2 00797-023 ad509 op amp 1/4 7400 7486 figure 22. phase-locked loop f/v conversion
ad650 rev. d | page 18 of 20 in signal recovery applications of a pll, the desired output signal is the voltage applied to the oscillator. in these situations, a linear relationship between the input frequency and the output voltage is desired; the ad650 makes a superb oscillator for fm demodulation. the wide dynamic range and outstanding linearity of the ad650 vfc allow simple embodiment of high performance analog signal isolation or telemetry systems. the circuit shown in figure 22 uses a digital phase detector that also provides proper feedback in the event of unequal frequencies. such phase-frequency detectors (pfds) are available in integrated form. for a full discussion of phase- lock loop circuits see phase lock techniques, 3 rd edition, by f.m. gardner, (john wiley & sons, inc., 1979). an analysis of this circuit must begin at the 7474 dual d flip flop. when the input carrier matches the output carrier in both phase and frequency, the q outputs of the flip flops rise at exactly the same time. with two zeros, and then two ones on the inputs of the exclusive or (xor) gate, the output remains low keeping the dmos fet switched off. also, the nand gate goes low resetting the flip-flops to zero. throughout this entire cycle, the dmos integrator gate remains off, allowing the voltage at the integrator output to remain unchanged from the previous cycle. however, if the input carrier leads the output carrier by a few degrees, the xor gate is turned on for the short time span that the two signals are mismatched. because q 2 is low during the mismatch time, a negative current is fed into the integrator, causing its output voltage to rise. this in turn increases the frequency of the ad650 slightly, driving the system towards synchronization. in a similar manner, if the input carrier lags the output carrier, the integrator is forced down slightly to synchronize the two signals. using a mathematical approach, the 25 a pulses from the phase detector are incorporated into the phase-detector gain (k d ). radian/amperes 104 2 a25 6 ? = = d k (9) also, the v/f converter is configured to produce 1 mhz in response to a 10 v input so its gain (ko) is secvolt radians 103.6 v10 hz1012 5 6 = = o k (10) the dynamics of the phase relationship between the input and output signals can be characterized as a second order system with natural frequency ( n ). c kk d o n = (11) and damping factor () is 2 d o kckr = (12) for the values shown in figure 22 , these relations simplify to a natural frequency of 35 khz with a damping factor of 0.8. for a simple approach to determine component values for other pll frequencies and vfc full-scale voltage, follow these steps: 1. determine k o (in units of radians per volt second) from the maximum input carrier frequency f max (in hertz) and the maximum output voltage v max . max max o v f k = 2 (13) 2. calculate a value for c based upon the desired loop bandwidth f n . note that this is the desired frequency range of the output signal. the loop bandwidth (f n ) is not the maximum carrier frequency (f max ). the signal can be very narrow even though it is transmitted over a 1 mhz carrier. secrad 101 7 2 = ? fv f k c n o (14) where: c units = farads f n units = hertz k o units = rad/volt sec 3. calculate r to yield a damping factor of approximately 0.8 using this equation: v k f r o n ? = rad 105.2 6 (15) where: r units = ohms f n units = hertz k o units = rad/volt sec if in actual operation the pll overshoots or hunts excessively before reaching a final value, the damping factor can be raised by increasing the value of r. conversely, if the pll is overdamped, a smaller value of r should be used.
ad650 rev. d | page 19 of 20 outline dimensions c ontrolling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents fo r reference only and are not appropriate for use in design . 14 1 7 8 0.310 (7.87) 0.220 (5.59) pin 1 0.080 (2.03) max 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc 0.150 (3.81) min 0.765 (19.43) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) figure 23. 14-lead side-brazed cera mic dual in-line package [sbdip] (d-14) dimensions shown in inches and (millimeters) compliant to jedec standards ms-001-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) pin 1 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 24. 14-lead plastic dual in-line package [pdip] (n-14) dimensions shown in inches and (millimeters)
ad650 rev. d | page 20 of 20 compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier figure 25. 20-lead plastic leaded chip carrier [plcc] (p-20a) dimensions shown in inches and (millimeters) ordering guide model gain tempco ppm/c 100 khz 1 mhz linearity temperature range package description package option ad650jn 150 typ 0.1% typ 0c to 70c 14-lead plastic dual in-line package [pdip] n-14 ad650jnz 1 150 typ 0.1% typ 0c to 70c 14-lead plastic dual in-line package [pdip] n-14 ad650kn 150 typ 0.1% max 0c to 70c 14-lead plastic dual in-line package [pdip] n-14 AD650KNZ 1 150 typ 0.1% max 0c to 70c 14-lead plastic dual in-line package [pdip] n-14 ad650jp 150 typ 0.1% typ 0c to 70c 20-lead plastic leaded chip carrier [plcc] p-20a ad650jpz 1 150 typ 0.1% typ 0c to 70c 20-lead plastic leaded chip carrier [plcc] p-20a ad650ad 150 max 0.1% typ ?25c to +85c 14-lead side-brazed ceramic dual in-line package [sbdip] d-14 ad650bd 150 max 0.1% max ?25c to +85c 14-lead side-brazed ceramic dual in-line package [sbdip] d-14 ad650sd 200 max 0.1% max ?55c to +125c 14-lead side-brazed ceramic dual in-line package [sbdip] d-14 ad650sd/883b 200 max 0.1% max ?55c to +125c 14-lead side-brazed ceramic dual in-line package [sbdip] d-14 ad650achips die 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c00797-0-3/06(d)

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